A self-biased PLL with current-mode filter for clock generation

A self-biased PLL with current mode filter is designed to achieve a bandwidth that scales with reference clock and is independent of PVT and multiplication factor. It provides wide tuning range with a simple robust structure. The 0.2mm/sup 2/ chip is fabricated in 0.35 /spl mu/m CMOS. Running at 800MHz, the phase jitter is 72.7ps/sub pp/ and the power consumption is 20mW.