A low-power multi-bit /spl Delta//spl Sigma/ modulator in 90nm digital CMOS without DEM

A 2/sup nd/-order 4b /spl Delta//spl Sigma/ modulator uses 3- and 5-level DAC. Truncating the ADC output while shaping and cancelling the error enables the use of low-resolution DAC and avoids DEM. The prototype is implemented in a 90nm digital CMOS technology and uses 2.1 mW from a 1.3V supply with a 40MHz clock. The SNDR is 52dB, 61dB and 72dB for an OSR of 10, 20 and 50, respectively.