Session 3 overview - backplane transceivers

The increasing clock rates of processing cores accompanying continuing advances in silicon technology drive the need to push electrical interconnect speeds higher. As industry-standard data rates pass 3Gb/s and approach the 5 to 12Gb/s realm, degradations from channel effects such as bandwidth loss, reflections, and crosstalk, can distort the signal to such an extent that robust data recovery requires equalizer-based backplane transceiver designs. Legacy 1 to 3Gb/s backplane channels rely on power-efficient NRZ transmit- and receive-side equalization techniques with adaptation. New signaling schemes, with better spectral efficiency, such as PAM4 and duobinary signaling, are of interest for data rates exceeding 10Gb/s. Another design challenge is the low bit-error-rate (BER) requirement of 10-15 or less.