Foreword - entering the nanoelectronic integrated-circiut era

Welcome to the ISSCC 2005, the foremost forum for the presentation of advances in solid-sate semiconductor circuits and systems. Paper submissions for this, the 52nd Conference, were at an all-time high of 579, a 25% increase from the 425 papers submitted last year. This year, the ISSCC program is the largest ever, with 233 technical papers presented in 31 regular sessions, with a three-paper Plenary Session to open the Conference. There are also eight Tutorials to chose from, five Special- Topic Evening Sessions, four Panel-Discussion Evening Sessions, five all-day Advanced-Circuit-Design Forums, and one allday Short Course, making this the most extensive program ever. As well, five DAC/ISSCC Student-Design-Contest winners will preside at poster presentations. The geographical distribution of the submitted technical papers illustrates the truly international character of the Conference: This year, 43% of the accepted papers are from North America, 23% from Europe, and 34% from the Far East. Of all of these, 59% are from industry, and 41% from universities. The Conference theme for 2005 is "Entering the Nanoelectronic Integrated-Circuit Era." With the emergence of integrated-circuits having transistor dimensions less than 100nm, integrated-circuit technology is moving from the microelectronic era into the nanoelectronic era. The indication that we have arrived at this major transition is given by the fact that this year's Conference has 55 papers covering new circuit techniques and devices that employ transistors with dimensions of 90nm or less. Digital chips with more than one billion transistors are now being realized, and novel circuit concepts using sub-100nm transistors are enabling both higher-performance and lower-power digital computation. In the analog-circuit arena, such transistor technology will lead to higher- speed analog-to-digital converters and enable new faster data-transmission rates for both wired and wireless communications. However, circuit design using transistors scaled below 100nm will require innovations that enable operation under decreasing nominal power-supply voltages, below 1.0V, and that meet the challenge of increasing device-parameter variations.