Intermodulation linearity characteristics of CMOS transistors in a 0.13 /spl mu/m process

This work presents experimental characterization of intermodulation linearity of CMOS transistors from a 0.13 /spl mu/m process. The IIP3 in the saturation region is shown to increase with V/sub ds/, even though g/sub m/ saturates. The IIP3 in strong inversion is found to be higher than the IIP3 at the well known linearity sweet spot near the threshold voltage. Longer channel transistors and thick oxide transistors are found to have linearity advantages. The results provide useful guidelines for optimal biasing and device selection in RFIC design.