Process technologies for high density, high speed 16 megabit dynamic RAM

This paper describes key points of submicron CMOS technologies for an experimental 16 Mbit DRAM fabrication. The memory cell and the transistor designs are most important to realize high density, high speed DRAMs. The main features of the technology are a new buried stacked capacitor cell and a high speed CMOS structure. The lithographic levels used were 0.7 µm for critical layers. The technologies have been verified using test vehicles and experimental 16 Mbit DRAM.