Electrostatic discharge protection for one micron CMOS devices and circuits

Scaling MOSFET's to one micron gate lengths and below has required the use of LDD and silicide clad source and drain diffusions. While these structural enhancements improve transistor performance and hot electron reliability they adversely effect ESD tolerance. In our experiments, we found that the use of silicide clad diffusions causes output buffer failure threshold levels to degrade by more than 50% from what is observed without silicided diffusions. In addition the use of the graded drain process, intended for hot electron suppression, causes a further degradation in the ESD protection level. For the first time we show that graded drain devices dissipate more power at a given current level when operating in the low impedance snap-back mode. In addition, experimental and theoretical results predicting ESD degradation due to the low resistance silicides are correlated with output buffer ESD performance. Finally, the role of the parasitic bipolar device, present in all CMOS output buffers, has been identified as providing an additional current path to ground during an electrostatic discharge.