A high-density, high-performance EEPROM cell

The theory, design, and performance data of a new high density, high performanee EEPROM cell is described. The memory cell is fabricated using standard n-channel double-polysilicon processing together with thin-oxide technology, and has an area of 24 × 24 µm2using 4-µm design rules. The cell is of the floating gate type, and employs avalanche injection of electrons and holes from a common injector. The use of thin oxide (≃ 100 Å) between the n⁺-p⁺injector region of the substrate and the floating gate of the memory transistor makes operation possible using voltages of less than 20 V. Write and erase times are 10 ms with an endurance to write-erase cycling of 10⁵cycles. The power dissipation during writing and erasing is 10 mW.