Vertical single-gate CMOS inverters on laser-processed multilayer substrates

Joint-gate, vertically stacked CMOS (JCMOS) inverters have been fabricated by a process which utilizes a multilayer substrate consisting of an oxidized n-type silicon wafer upon which are deposited two uniformly p-doped polysilicon films separated by a thermally grown (gate quality) oxide. The upper polysilicon film is re crystallized by a scanning CW argon laser and serves as the nMOS substrate. The lower film is the joint polysilicon gate and is heavily doped p-type rather than n-type in order to allow fabrication of enhancement-mode nMOS devices with reduced vertical electric field after threshold voltage adjustment by ion implantation. Fabrication proceeds using a six-mask, self-aligned, top-down process. The W/L ratio was 88 µm/38 µm for the nMOS upper device and 88 µm/60 µm for the pMOS lower device. By virtue of the self-aligned process, both devices can be scaled to smaller dimensions, yielding approximately a 40 × 8 µm inverter in 4 µm channel length technology.