Bit by bit erasable E2PROM with single transistor per bit

An electrically-erasable floating-gate PROM cell utilizing three levels of polysilicon is described. The cell is programmed via a channel injection mechanism similar to EPROM's Erasure is accomplished with the first-level of poly-silicon which serves as an erase electrode causing field emission of electrons from the bottom of the second-level floating gate. In this new cell structure, memory can be erased bit by bit or word by word, and the stored charge in the floating gate can be checked quantitatively by applying sensing voltage to the first poly-Si gate which is also used as erase gate. New fabrication process, mechanism of bit by bit electrically erasing and design theory of the new memory cell are also described.