A model of write-inhibition in dynamic injection MNOS

Dynamic Injection MNOS (DIMNOS) memory devices feature high-speed writing, 5-V drain voltage, and MNOS backup one-transistor-type dynamic RAM's. They are written on MNOS, like conventional one-transistor-type dynamic RAM's, when high writing voltage is applied to the MNOS gate. In experiments with DIMNOS, the threshold-voltage shift (\Delta V_{th}) of MNOS in the writing mode does not depend very much on temperature;\Delta V_{th}in the write-inhibited mode depends hardly at all on temperature; and\Delta V_{th}in the write-inhibited mode decreases under the condition that the product of the number of attempts and pulsewidth is constant when he pulsewidth is longer than 10^-4s. The proposed model in the write-inhibited mode means that weak avalanche occurs due to field concentration between the control transistor and MNOS memory region. As a result, hot electrons are injected between the ultrathin SiO2and Si3N4films of MNOS. This model is supported by the above mentioned experimental results in the write-inhibited mode.