A new CML memory cell for high density memory devices

A new CML cell structure is realized by introducing a new configuration for the load resistors in a cell. The load resistors are vertically integrated within multi-emitter transistor, resulting in a very small cell area. The cell size of 960 µm²is obtained by using 2 µm design rule, which is approximately 60% of the Schottky load cell. The operation of new cell is demonstrated by 1k bit CML RAM.