A new submicrometer channel/High-speed MOS-LSI technology

A new self-aligned submicrometer channel length (0.25 to 0.86 µm) MOS device (SMOS) and its application to integrated-circuit technology are proposed and demonstrated. The self-aligned SMOS structure has been developed by a double ion implantation of boron and arsenic through a specific bird's beak shape of continuous oxide thickness change created by LOCOS oxidation techniques. SMOS showed a gate threshold voltage of 0.6 to 1.0 V, breakdown voltages of 12-16 V, and a transconductance approximately three times larger than 2-µm channel MOS devices. A 21-stage ring oscillator with an enhancement/depletion (E/D) mode inverter showed typical delay times of 0.8 to 1.8 ns per gate and power dissipation per gate of 0.2 to 0.6 mW. It can be expected from a comparison of the device structures that the SMOS might have up to 15-50 percent higher packing density than in DMOS and VMOS in most kinds of recent logic and memory integrated circuits.