Low-voltage CMOS charge-pump PLL architecture for low jitter operation

This paper presents circuit level techniques that reduce both intrinsic and supply or substrate injected noise of charge-pump PLLs operating in the noisy environment of mixed analog-digital ICs. Using a ripple-pole-less sample-reset loop filter provides a staircase shaped oscillator control current that reduces the reference spur, and a nearly 90° phase margin that leads to a negligible jitter peaking and locking overshoot. A fully differential loop filter having low-VT devices and accumulation MOS capacitors in the signal path was used to minimize the substrate and supply injected noise. Oscillator's PSRR is improved using differential inverters and clamping its amplitude to supply independent voltage levels. The proposed methods are validated through measurements on two PLLs: a reference one using a feed-forward architecture and a low jitter one using a sample-reset architecture.