LVDS I/O cells with rail-to-rail receiver input for SONET/SDH at 1.25Gb/s

Low voltage differential signaling (LVDS) has developed as a data transmission standard for on-chip, on-board/backplane or cable connections. This paper reports design criteria and measurement results of 1.25Gb/s LVDS I/O cells serving various application requirements (e.g., SONET/SDH), developed for 0.25µm and 0.18µm standard digital CMOS processes. Especially the design of a rail-to-rail input stage is described.