A 1.8V 20mW 1mm214b 100Msample/s CMOS DAC

A binary weighted current steering DAC is a power-efficient architecture, because almost all the current taken from the supply is used for the output signal. Typically, the architecture suffers from poor linearity characteristics, but the problem can be prevented with a new calibration method, where the currents generated for the most-significant bits are fine-tuned. As a result, a very compact and low-power solution can be implemented by using a low-voltage digital technology.