A 2.0Gbps multiplexer and a 2.7Gbps demultiplexer using 0.35 µm SOI-CMOS technology

This paper describes a 4:1 multiplexer and a 1:4 demultiplexer using 0.35µm SOI-CMOS technology for ultra high-speed telecommunication system LSIs. The multiplexer adopts a shift register architecture with a modified counter operating stably at high-frequency, while the demultiplexer adopts a 2-bit tree architecture. The multiplexer and the demultiplexer uses double-rail flip-flop circuits which can operate at high-frequency due to their reduced parasitic capacitances. The multiplexer operates at 2.0 Gbps dissipating 122 mW and the demultiplexer operates at 2.7 Gbps with 128 mW at a 2.0V supply voltage.