A 155 Mbit/s fully digital bit synchronizer

In this paper we describe a circuit operating at 155 Mbit/s for the alignment of a clock to a continuos or bursty data flow. Possible drifts, jitter and wander are taken into account. The alignment method allows a fully digital implementation, with a reduced cost and high speed performance in line with common telecom specifications (ATM, SDH). The circuit has been realized in a 0.45µm CMOS Gate Array technology.