R, G, B acquisition interface with line locked clock generator, for LCD driver

This paper presents the analysis, design and experimental results of a triple 8 bits, 80 MSample/s Analogue-to-Digital acquisition channel with gain and clamp controls, together with a sample clock regenerator. While today's LCD driver systems require some 10 analogue integrated circuits, this single chip offers three 7.4 effective bits 300 MHz bandwidth acquisition channels, sampled by a 250 ps rms long-term jitter regenerated clock. This new level of integration and performances is reached through the implementation of a new clock regenerator architecture. The integrated circuit, available in a 100-pins plastic package, is realised in a 13 GHz, 1 µm BiCMOS process and measures 25 mm². It dissipates 1 W from 5 V supplies.