Characterization of various etching techniques for gate level failure analysis and substrate decoration for advanced Cu/low k technologies

In this paper, VLSI technology scaling trends and challenges will be addressed. Failure analysis (FA) challenges, and failure modes for advanced technologies will also be presented. Both Cu/low k integration and gate dielectric integration issues will be discussed, followed by characterization of various poly-silicon etches used for gate oxide decoration. Finally, several different silicon substrate decoration techniques will be presented.