Clock and data recovery with adaptive loop gain for spread spectrum SerDes applications

A novel clock and data recovery architecture with adaptive loop gain is proposed for spread spectrum SerDes (serializer/deserializer) applications such as serial AT attachment. The proposed design consists of a half-rate Alexander phase detector, a phase-shifting phase interpolator with a frequency differentiator and an adaptive loop gain filter. The frequency differentiator determines the clock rate difference between the referenced clock and the recovered clock. This value is then used to adjust the gain of the adaptive loop filter for better acquisition of lock with minimized jitter. The proposed design can be implemented in a digital CMOS process which reduces the design difficulty and cost. System operation has been verified using the Cadence SpectreRF and Verilog-A simulators. The results show that the system is capable of recovering /spl plusmn/5000 ppm spread spectrum data with up to a maximum of 0.5 UI of deterministic jitter.