Design techniques for low-power cascaded CML gates

In this paper, design techniques for cascaded current mode logic (CML) gates are proposed. Criteria to size each gate bias current in a cascade of CML gates are derived in practical design cases, i.e. when a high speed or a low power consumption is targeted. The analytical results are simple. Design examples based on a 20 GHz bipolar process are presented to clarify and validate the procedure.