A new RSA encryption architecture and hardware implementation based on optimized Montgomery multiplication

RSA is a widely acceptable and well used algorithm in many security applications. Its main mathematical function is the demanding, in terms of speed, operation of modular exponentiation. In this paper a systolic, scalable, redundant carry-save modular multiplier and an RSA encryption architecture are proposed using the Montgomery modular multiplication algorithm. By completely avoiding the transformations from redundant to non-redundant numbers at the intermediate stages of the architectures, the need for addition is eliminated and very interesting results, in terms of clock frequency, throughput and chip covered area, are achieved.