Low-voltage micropower multipliers with reduced spurious switching

We describe micropower low-voltage (1.1V) low switching activity array multipliers for power-critical low speed (/spl les/5MHz) applications. These multipliers feature the lowest power dissipation (18.8 /spl mu/W/MHz or /spl sim/32% lower for 16-bit and 76.7 /spl mu/W/MHz or /spl sim/53% lower for 32-bit) and lowest energy-delay-product (but slightly reduced speed) of all multipliers compared by using a 0.35 /spl mu/m CMOS process. We obtain these attributes by virtually eliminating the spurious switching by means of proposed latch adders and chronologically timing their assertions by means of delay circuits. We also analyze the switching activity of the different multipliers and verify our results based on the post-layout computer simulations and on measurements on prototype IC.