Glitch-free discretely programmable clock generation on chip

In this paper we describe a solution for a glitch-free discretely programmable clock generation unit (DPGC). The scheme is compatible with a GALS communication scheme in the sense that clock gating and clock pausing are possible. Besides, the proposed scheme does not require waiting for a new clock as the frequency change is seen as almost instantaneously. A prototype has been designed for a 0.13/spl mu/m triple-well CMOS process technology to also study the properties of the scheme with respect to voltage scaling.