The DRS2 chip: a 4.5 GHz waveform digitizing chip for the MEG experiment

A switched-capacitor array (SCA) chip is currently under development for fast waveform digitizing of PMT and drift chamber signals for the MEG experiment at PSI, Switzerland. This experiment searches for the lepton-flavor violating decay /spl mu//sup +/ /spl rarr/ e/sup +//spl gamma/ with a sensitivity down to 10/sup -13/. After a first prototype (DRS1), the second prototype chip (DRS2) has been fabricated in a 0.25 /spl mu/m CMOS process and successfully been tested. It contains 10 channels, each with 1024 capacitive sampling cells. Waveform digitizing takes place with an on-chip generated frequency ranging from 0.5 GHz to 4.5 GHz. The cells are read out at 40 MHz with an external 12 bit flash ADC. A phase-locked-loop circuit (PLL) ensures high stability, making the chip suitable to replace both ADCs and TDCs in an experiment with a timing resolution below 100 ps and an ADC resolution equivalent of 14 bit. The design of the chip is described and results from performance measurements are reported. Ideas of fast online waveform processing are discussed.