MOSFET optimization in deep submicron technology for charge amplifiers

The optimization of the input MOSFET for charge amplifiers in deep submicron technologies is discussed. After a review of the traditional approach, the impact of properly modeling the equivalent series noise and gate capacitance of the MOSFET is presented. It is shown that the minimum channel length and the maximum available power are not always the best choice in terms of resolution. Also, in an optimized front-end, the low frequency noise contribution to the equivalent noise charge may depend on the time constant of the filter. As an example, results from the commercial TSMC 0.25 /spl mu/m CMOS technology are reported.