Impact ionization in saturated high-voltage LDD lateral DMOS FETs

The mechanism of impact ionization in high-voltage lightly-doped drain (LDD) lateral DMOS FETs is analyzed. Two-carrier PISCES simulations confirm a reduction in both sustaining voltage and output impedance compared to zero or one-carrier simulations. Maximum impact ionization is not observed at the peak field location, but as an interaction of subsurface conduction and a high-field region located under the gate field plate. An extended gate field plate is shown to reduce pre-avalanche impact ionization without substantially degrading avalanche breakdown. Breakdown optimizing design methodologies are shown to be inadequate to guarantee minimal impact ionization. Finally, the reduction in saturated output impedance predicted by PISCES is confirmed on 500-V fabricated devices.<>