Hardware results demonstrating defect detection using power supply signal measurements

The power supply transient signal (I/sub DDT/) method that we propose for defect detection analyzes regional signal variations introduced by defects at a set of power supply pads on the chip under test (CUT). The method is based on the comparison of the CUT with chips that are known to be defect free. A set of defect free chips are analyzed to establish a statistical metric that distinguishes between defect effects and process variation (defect free) effects. This paper presents hardware results that demonstrate the effectiveness of a novel geometry based defect detection technique using nine copies of a test chip. Eight chips are used as defect free chips to derive the statistical limits. Emulated defects are provoked in the ninth chip to evaluate the defect detection capabilities of the method.