Root raised cosine filter for a WCDMA receiver using distributed arithmetic for power optimization and enhanced speed

A digital decimation and channel selection filter for a WCDMA receiver is presented. A rectangular pulse root raised cosine filter was used as the required channel selection filter. The filter was designed to process the output from a modulator, suppressing the out-of-band quantization noise, interfering channels and operating as a matched filter. Polyphase half-band structures, with distributed arithmetic based look up table structures, were used to minimize the power consumption and increase speed at the cost of area. The proposed filter was implemented in Verilog HDL using a Spartan FPGA chip.