Design of a CPPLL-based clock multiplier for USB hub

This paper describes the design and implementation of a clock multiplier circuit used as a part of a USB hub chip set. It obtains a precise 48 MHz internal system clock signals from a 6 MHz off-chip reference clock by using a charge pump phase locked loop (PLL) as a multiplier. In addition, the output internal clock signals can be altered from 36 MHz to 96MHz by changing the control signals. The USB hub clock architecture, module circuits of PLL design, simulation results, and chip layout are included. Experimental results using CSMC 0.6 /spl mu/m process technology show that the required timing relations can be obtained.