Optimal wire sizing in early-stage design of on-chip power/ground (P/G) networks

Due to decreasing supply voltages and increasing power consumption of today's VLSI chips, IR drops on on-chip power/ground (P/G) grids have to be explicitly considered during the floorplanning stage in today's physical design flow. Thus, it is very important to size the P/G grids in the floorplanning to efficiently minimize the worst-case IR drop subject to limited routing resource in early-stage P/G network design. In this paper we first present the optimization problem of mesh-structured center-bumped P/G grids under given routing resources. We then propose an efficient wire sizing method based on an incomplete Cholesky conjugate gradient (ICCG) simulation method to obtain the optimal solution for mesh-structured P/G grids. After this we improve the simulation method by using a novel simulation method, named approximate current distribution (ACD), to speedup the optimization. Finally we present a closed-form expression to directly calculate the optimal sizes of P/G grids given the current distributions computed from ACD. Experimental results show that the optimization cost function has one global minimum with respect to the width ratio. The theoretically computed optimal solutions match very well with the simulated results, which can lead to significant speedup in future IR-drop aware floorplanning.