Design of CMOS magnetic sensor integrated circuit

A new CMOS magnetic sensor integrated circuit has been developed in a 0.6 /spl mu/m CMOS technology. The single chip integration of the split-drain magnetic field-effect transistor (MAGFET) and the subsequent signal processing circuits are realized. With the pre-processing circuit and correlated double sampling (CDS) circuits, the fixed pattern noise (FPN) is greatly reduced. The MAGFET is sectorial, with a radius of 48 /spl mu/m and an angle of 90/spl deg/. The relative sensitivity of the magnetic sensor can be 87.3 mV/(T/spl middot//spl mu/s).