A novel single poly EEPROM cell structure on thin oxide tunnel technology

This paper presents a single poly EEPROM cell structure on thin oxide tunnel technology. It consists of adjacently placed burial N+ diffusion capacitance and single poly EEPROM transistor which has a thin oxide tunnel (about 90 /spl Aring/). The common poly of the stack capacitance and the transistor works as a "floating gate". The burial N/sup +/ diffusion of capacitance as "control node (gate)", Test chips which were fabricated in a 1.2 /spl mu/m/150 /spl Aring/ single poly process showed 4-9 V of threshold voltage shift and more than 100,000 cycles of endurance. This EEPROM cell can be easily integrated with CMOS digital and analog circuits.