CMOS transistor design challenges for mobile and digital consumer applications

CMOS transistor design for low power applications poses significant challenges. The rich features now required in mobile phones and PDAs call for complex computations and ever-increasing processing power. At the same time, low power consumption continues to be an essential requirement to ensure usable battery life for mobile and portable products. This paper examines challenges associated with transistor scaling to meet both performance and leakage power targets. A methodology to co-optimize transistor and circuit design is discussed. Various aspects of CMOS transistor scaling are discussed in consideration of both optimized power and performance. Transistor static leakage components, including gate leakage (Ig), subthreshold leakage (Ioffs), and source/drain gate edge diode leakage (Igdl), are separately studied and examined. We show that the optimal transistor targeting requires defining transistor leakage specs in conjunction with power management schemes used in circuit designs. Cost containment for mobile and consumer digital application chips is of paramount importance. SRAM bit cell area has a significant impact on overall chip sizes. Random dopant fluctuation (RDF), narrow width effects, and other transistor scaling issues affecting cell stability and manufacturability, are discussed.