Performance and power analysis of asynchronous pipeline design methods

In this paper, ten asynchronous pipeline styles are studied and compared. These include GasP, MOUSETRAP, IPCMOS, LP/sub SR/2/1, LP/sub HC/, STFB, LDA, LP2/1, RSPCFB and NCL. The first five designs are based on bundled-data (BD) category while the last five are based on data-driven (DD) category. Analytical expressions for the throughput and the latency of the asynchronous styles are presented. A 4-bit 4-stage FIFO circuit based on each style is designed and simulated utilizing HSPICE with a 0.18 /spl mu/m CMOS technology. The simulation results are then used to compare the FIFOs in terms of throughput, latency, power dissipation and transistor count.