A low-power low-voltage fully digital compatible analog-to-digital converter

This paper describes the circuit design and architecture of a fully digital compatible analog-to-digital converter (ADC). The used architecture is based on current-mode cyclic algorithmic ADC where a digital calibration scheme based on adaptive algorithm is used to help to alleviate and compensate the precision requirements in the analog domain. The propose architecture can achieve high-speed and high-accuracy at low voltage power supplies with ultra low power dissipation and it does not require good device matching. The low-power digital compatible ADC has been simulated in a 0.18-/spl mu/m CMOS process. Using a 1.5-V power supply it achieves a dynamic range of 75-dB and the analog part of system dissipates only 0.9-mW.