A throughput/complexity analysis for the VLSI implementation of LDPC decoder

This paper presents an analysis of the VLSI complexity of different LDPC decoder implementations. Both fully parallel and serial solutions are considered and compared in terms of architectural issues, hardware complexity, power consumption and supported throughput. To provide numeric results a 1/2 rate, (3,6) regular LDPC code with a 2048 codeword has been considered and area complexity estimations have been carried out with reference to a 0.18 /spl mu/m standard-cell CMOS technology.