A programmable time measurement architecture for embedded memory characterization

This paper describes a programmable time measurement architecture that facilitates memory characterization. We have created a standalone time measurement architecture that can measure rise time, fall time, pulse width and propagation delay time measurements without the need of additional circuitry as presented in M. J. Hsiaoet al. (2004) or circuit duplication based in T. Xia and J. C. Lo (2003). This is achieved by the use of time-to-digital conversion (TDC) based on the dual-slope principle. The key feature of the proposed architecture is programmability through the use of a novel programmable input stage. Furthermore, a current steering time-to-voltage converter (TVC) is used in order to improve the linearity and dynamic range as compared to recent designs. The proposed architecture has been designed using 0.18/spl mu/m CMOS process and results from simulations using foundry models suggest it is possible to achieve a timing resolution of 103ps. The measurement core size is 110/spl mu/m /spl times/ 75 /spl mu/m.