FPGA based fault emulation of synchronous sequential circuits

This paper describes a feasibility study of accelerating fault simulation by emulation on FPGA. Fault simulation b an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to further speed up simulation, we propose to make use of reconfigurable hardware by emulating circuit together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms.