A double level metallization system having 2 mu m pitch for both levels

A double-layer metal (DLM) process having 2- mu m pitch for both metal levels has been successfully developed. This DLM system has been used in a 0.7- mu m CMOS process to fabricate 1-M SRAM and 256 K SRAM devices. Some relevant design rules are 1- mu m metal line and space for both levels, and 0.9- mu m contact and via openings. To meet these requirements, the process features planarization to minimize topology at LOCOS, polysilicon, and metal levels. The technological results are presented as well as reliability and electrical results. Photographs of fully processed and functional 256 K and 1-M high-performance SRAMs are shown.<>