Logic synthesis and technology mapping of MUX-based FPGAs for high performance and low power

The problem of logic synthesis and technology mapping for Actel-1 MUX-based FPGAs in the context of low power applications has been addressed in this paper. Decomposed BDD representation, which helps to deal with large Boolean functions, has been used in the technology independent as well as technology mapping phases of the proposed synthesis approach. To minimize area, delay and power dissipation of the realized circuits, several novel optimization techniques have been adopted in both the phases. Efficacy of the proposed approach has been demonstrated with the help of experimental results on a large number of ISCAS benchmark circuits.