Circuit design to achieve whole-chip ESD protection for UXGA/HDTV LCOS IC product

Successful circuit design to achieve the whole-chip electrostatic discharge (ESD) protection for an UXGA/HDTV LCoS IC product with a die size of 20289.6 /spl mu/m/spl times/16841.5 /spl mu/m has been proposed and practically verified in 0.35-/spl mu/m 3.3 V/12 V CMOS process. This LCoS IC with both low-voltage (LV) and high-voltage (HV) ESD protection circuits can sustain ESD stresses of 3.5 kV and 200 V in human-body-model (HBM) and machine-model (MM) ESD test standards, respectively.