I/O translation circuits for a systolic RNS matrix multiplier

I/O translation circuits designed for a special purpose array processor for fast matrix multiplication based on RNS are presented. The design approaches are pipelining, regularity and repeatedly using circuit blocks found inside the systolic cells, and thus reducing the design time and maximizing the performance. The mathematical operations of addition and multiplication are simpler than residue division and sign determination. The matrix multiplication algorithm is an ideal candidate, since it only requires multiplication and addition. This design methodology also achieves a higher chip density.<>