A high-performance architecture of arithmetic coder in JPEG2000

This paper presents a high-performance architecture of the arithmetic coder for the embedded block coding algorithm in JPEG2000. The dedicated pipeline architecture, enhanced by the inverse multiple branch selection (IMBS) method, is proposed to code two context-symbol pairs per clock cycle. The overall design was implemented in VHDL and synthesized for FPGA devices. Simulation results show that it can process about 17 million samples at 77 MHz working frequency