Design and simulation difference types CMOS phase frequency detector for high speed and low jitter PLL

This paper presents the different design schemes of the phase frequency detector (PFD) and compares the output simulation results. The circuits that have been considered are the standard CMOS (S/spl I.bar/PFD), true single-phase clock PFD (TSPC/spl I.bar/PFD), DCVSL differential cascode voltage switch logic PFD (DCVSL/spl I.bar/PFD) and current mode logic PFD (CML/spl I.bar/PFD). The simulation results are focused on exploring the dead zone, high frequency operation, power dissipation and phase noise of the different PFD. The results reported in this paper based on simulation done using SpectreS extracted layout. The different circuits of PFD are designed using 0.35 /spl mu/m CMOS technology with 3.3V supply voltage.