ASIC design of the linearisation circuit of a PTC thermistor

The paper describes the ASIC (Application Specific Integrated Circuit) design of the linearization circuit of a PTC thermistor sensor. The linearizer circuit is based on the use of a ratio-logarithmic amplifier. The basic idea is to logarithmically linearize the exponential input-output relationship of PTC thermistor sensor. Compared to other conventional techniques, viz. look up table method, polygon interpolation method, polynomial interpolation method, method of linearization using programmable gain amplifiers, the scheme provides a low cost simple alternative technique of linearization, linearizing the PTC thermistor voltage output signals to a high accuracy. Further, CMOS circuits have been used to have a minimal power dissipation of the circuit. The circuit is found to dissipate a power of 3.125 mW in a supply voltage of 5 Volts. A SPICE model of a PTC thermistor has also been developed. The entire scheme has been done using the TSPICE software.