Reliability failure induced by the Si epitaxy growth on PMOS high voltage oxide in 0.15/spl mu/m embedded flash memory devices

It is discovered that Si Epitaxy causes charge to breakdown (Qbd) failure of mainly high voltage (HV) PMOS capacitors at shallow trench isolation (STI) intensive structure during the qualification of 0.15um embedded Flash memory process, and this Qbd failure rate is strongly related to the densification anneal process for STI gapfill oxide. It is confirmed that the higher thermal stress, the higher the Qbd failure rate. Even though the mechanism of Si epitaxy growth is not fully understood, the process induced stress at the corner of STI should be a major factor. The driving force of this stress induced Si epitaxy (SISE) is a localized thermodynamical instability. This SISE can be suppressed with lower thermal budget using rapid temperature anneal (RTA) for the densification of HDP oxides, instead of the furnace anneal in our 0.15um embedded Flash memory process. Furthermore, the missing Co silicide has been discovered precisely above the location of the SISE, and this missing silicide is strongly suspected to be correlated to SISE growth. We propose that the SISE induced high compressive stress causes the Co silicide to decompose into Co and Si to reduce the free energy of the poly gate/Co silicide region.