Testing and diagnosis techniques for LUT-based FPGA's

In this paper, a ping-pong type fault detection and fault diagnosis technique for field programmable gate arrays (FPGAs) is proposed. Efficient (k + 1) test configurations for a single configurable logic block (CLB) are first derived and proved that 100 % fault coverage can be obtained, k denotes the number of inputs of an LUT. Thereafter, the whole CLB array is divided into cell groups and each group contains 2 cells-the master cell and the slave cell. Since both cells can be used as the test pattern generator (TPG) and the block under test (BUT) at the same time, one test session is required instead of two test sessions for traditional fault detection techniques. Therefore, the test complexity is reduced significantly. Multiple fault detection and location can be easily achieved. Since the number of test sessions is less than the traditional approaches, significant speedup can be obtained. Comparisons with other works based on detection and diagnosis complexity are also given.