A systematic way of functional testing for VLSI chips

In VLSI chips, the detail circuit implementation is always unknown; only the functional behavior could be known to the users. In this paper, we present a systematic technique for detecting and locating of both stuck-at and bridging faults on the primary input and output lines based on the functional behavior of the circuit being tested. The proposed technique could be quite helpful for both the academic and industrial users of VLSI chips for their testing of the stuck-at and bridging faults and verifying the functions before the chips are applied. Algorithms and experimental results of computer implementation of the scheme are reported.